In at least certain other approaches, it is believed that enable signals for clocks have not been required to "stop" domino logic circuits in their precharge states. In the context of a low-voltage-swing bus, however, if the enable signals for the clocks are not used to stop the domino logic circuits in their precharge states, then any delay associated with coming out of the precharge states may not be sufficiently well controlled. Also, in the context of wide ANDing tasks, such as in a carry-skip adder application, using non-ratioed NOR gates may not provide sufficiently fast performance, especially in the context of low-voltage-swing topologies and applications.
In particular, logic arrangements that use pulse clocks may be useful in certain applications. An example of the use of pulse clocks in a logic arrangement, which is a domino logic arrangement, and is shown, for example, in commonly assigned U.S. Pat. No. 5,880,608, which concerns a method of interfacing a static logic arrangement to a dynamic domino logic arrangement. In particular, a static logic arrangement is connected to one input of a domino evaluation logic arrangement. The domino evaluation logic arrangement only operates during a relatively brief time interval or window, which occurs while an evaluation control arrangement is in its "on" state. Since the input to the domino gate need only be stable during this time interval or window, the output of the static logic arrangement does not have to be latched. Since advanced micro-architectures may require a number of "pipeline" stages and a number of corresponding data latches, which may consume integrated circuit power consumption and area, to interface the various pipeline stages, the foregoing pulse domino logic arrangement is intended to reduce the number of such data latches.
Another example of an arrangement using pulsed clocks may be found in commonly assigned U.S. Pat. No. 5,942,917, which is entitled "High Speed Ratioed CMOS Logic Structures For A Pulsed Input Environment." In particular, this patent concerns a complementary-metal-oxide-semiconductor field-effect-transistor (CMOSFET) logic structure that is adapted to receive pulsed active input signals and to provide a logical output with a relatively small switching delay. The pull-down transistors and complementary pull-down transistors are ratioed so that the default logical output level remains relatively close to a nominal level when the logic structure sinks or sources a direct current. Also, when the pulsed input signals are inactive, no direct current path is enabled. In an exemplary embodiment, a logic structure, which has PMOSFET pull-up devices and NMOSFET pull-down devices, receives active low pulsed input signals and produces a high logic output signal when all the input signals are at a low logic level. When at least one but not all of the input signals are low, the logic structure provides a low logic output signal and sinks a direct current. When all of the input signals are at a high logic level, the logic structure produces a low logic output signal and no direct current paths are switched on.
As regards passgate logic, passgate switching networks have been used to implement relaying logic by using passgate transistors, such as MOSFET devices, and standard clocking arrangements. In particular, such switch networks may use a plurality of passgate transistors in a chain to connect conditionally two nodes, such as an input node and an output node, together. That is, passgate switching networks may be used when the logic function may be considered to consist of signals that are to be relayed or steered conditionally through the switching network.
Low voltage swing ("low-voltage-swing" or "LVS") logic arrangements may provide a faster data throughput than fill voltage swing ("full-voltage-swing" or "FS") logic arrangements depending on the specifics of the application. In a full-voltage-swing logic arrangement, a true input data signal must transition between a full high logic level, such as a supply voltage (Vcc or Vdd), and a full low logic level, such as a relative ground (true ground or Vss), before the full-voltage-swing logic arrangement may provide a valid data output signal. By contrast, a low-voltage-swing logic arrangement may provide valid data output signals based on a difference in potential between a pair of complementary data input signals. This potential difference may be relatively small, and may be, for example, on the order of about 100 millivolts.
More specifically, low-voltage-swing logic arrangements carry valid data signals on a pair of data "wires". A first data wire is used to carry a true value of the valid data signal and a second data wire is used to carry a complementary value of the same valid data signal. In a two-phase clocking arrangement, during a first clocking or pre-charging phase, both the data wires are pre-charged to a predetermined or pre-charge potential. At this point, the data wires do not contain any valid data or information. During a second clocking or evaluating phase, the potentials on the two wires may diverge in response to the information content of an input data signal. In particular, one data wire "evaluates" by transitioning toward an evaluation potential and the second data wire remains at the pre-charge potential, the low-voltage-swing logic arrangement then provides a valid data output signal based on the potential or voltage difference between the valid true and complementary data input signals. After the second clocking or evaluating phase, both data wires are again pre-charged to their pre-charge potential during a succeeding first clocking or pre-charge phase.
Accordingly, low-voltage-swing logic arrangements may operate faster than corresponding full-voltage-swing logic arrangements so as to provide an improved level of valid data throughput. Also, since low-voltage-swing logic arrangements do not require full-voltage-swing transitions to provide valid data output signals, the signal voltages used in a low-voltage-swing logic arrangement may be lower than corresponding full-voltage-swing logic arrangements. As a result, the use of low-voltage swing logic arrangements may provide reduced power consumption, as compared to a full-voltage-swing logic arrangement, in an integrated circuit arrangement, such as, for example, a microprocessor, or any other suitably appropriate semiconductor-based logic arrangement.
In certain integrated circuit arrangements, including, for example, microprocessors and any other suitably appropriate logic arrangements, one or more fixed delay arrangements or devices may be provided to better ensure that a clock signal does not arrive before the data in a data path of a particular logic arrangement. In some self-timed circuits, for example, one or more fixed delay devices may be arranged in the clock path to delay the clock signal with respect to the data signal in the corresponding data path of some logic arrangement. The clock signal may, for example, be delayed by arranging fixed gate delays, such as MOSFET-based inverter-buffer devices in the clock signal path. In this way, a suitably appropriate "race margin" may be added to the logic arrangement to account for any timing variations between a clock signal in the clock signal path and a valid data signal in the corresponding data path of the logic arrangement, such as a data path in a complementary or differential domino logic arrangement. Such a race margin may, for example, be on the order of about five (5) sigma variations depending on the particular application, the semiconductor materials used and the gate device structure used in the logic arrangement to meet the yield requirements for a product.
An example of the use of fixed delay devices in a clock signal path of a logic arrangement may be found in commonly assigned U.S. Pat. No. 5,453,708, in which a clocking scheme provides for an improved latching of an output from a domino logic arrangement by delaying a pre-charging of a data node in the domino logic arrangement. In particular, the pre-charging delay is achieved by introducing the delay in the clocking circuit arrangement, which activates the pre-charging of the domino node. No delay is introduced in the data path so that the evaluation and transmission of the data signal is not delayed. Thus, during a first phase of a clocking cycle, the domino node is pre-charged to a predetermined logic state. Also, during this pre-charge phase, an input latch couples an input data signal to the domino logic arrangement. During a second phase of the clocking cycle, the domino logic arrangement performs a logic operation based on the input data signal, and an output latch latches the logic state of the domino output for transmission from the output latch. Subsequently, when the pre-charging phase begins again, the pre-charging of the domino node is delayed by a fixed time until the output latch is completely de-activated so as to better ensure that the pre-charge potential is not latched out so as to corrupt the data being output.
Also, delay lock loop ("DLL") circuits and techniques may be used in an integrated circuit arrangement to implement a faster reference clock signal that is based on a slower base or external clock signal, which is sourced externally to the integrated circuit arrangement. The faster reference clock may then be provided to different functional unit blocks of the integrated circuit arrangement. Examples of such an arrangement may be found in commonly assigned U.S. Pat. Nos. 5,537,068 and 5,828,250. It is believed that such an arrangement may conserve power by providing clock startup and stop times, which may be faster than that provided by phase-locked-loop ("PLL") techniques, which may also be used to provide a reference clock signal based on an external clock signal.
Additionally, differential cascode voltage structures have been used in which the gate of a first pull-up PMOSFET device, which is coupled to an NMOSFET device-based true input pull-down logic network, is coupled to a complementary output of an NMOSFET device-based complementary input pull-down logic network and to a drain of a second pull-up PMOSFET device. The differential cascode voltage structure is further defined by having a gate of the second pull-up PMOSFET device, which is coupled to the NMOSFET device based complementary input pull-down logic network, that is coupled to a true output of the NMOSFET device-based true input pull-down logic network and to a drain of the second pull-up PMOSFET device, and in which the sources of the first and second PMOSFET pull-up devices are coupled to a supply voltage and the logic networks are coupled to ground. In particular, in such differential cascode voltage structures, exactly one of either the true or complementary NMOSFET device-based pull-down logic networks will complete a path to the power supply. Additionally, the NMOSFET device-based pull-down network will lower the output voltage, which will turn on the other pull-up PMOSFET device and which will also turn off the pull-up PMOSFET device that is being driven to its low logic level.
As regards all of the above, it is not believed that any of these systems reflect the advantages, apparatuses, methods, structures or topologies of the present inventions, which are discussed below.